Investigation of Long-Term SPI NOR Flash Timing Behavior

• Typ der Arbeit: Masterarbeit
• Status der Arbeit: reserviert
• Betreuer: Yannick Loeck

Basic Tasks:

• pick out around 5 different large (>=128MiB) SPI NOR flash chips
• identify their theoretical timing from the datasheet and later from the SFDP table
• develop a test bench PCB in the form of a nucleo shield
• benchmark/stress test the chips to identify real timing
• compare to theoretical values, and among each other

Timing Parameters:

• byte up to page read, continuous read if applicable
• byte up to page write, continuous write if applicable
• sector (and larger block if applicable) erase
• chip erase

Parameter Space:

• chip fill level
• data patterns
• cell wear
• data location on chip
• temperature
• on-chip ECC?
• voltage

Think about:

• where to log the results (UART, additional non-volatile storage, ...)
• how to store each chip's (sector's?) wear level persistently